Proposed response to your P1076 ballot comment

Dear Dr Hanna,

Thank you for participating in the recent IEEE ballot on the revision of the
VHDL standard. As part of the ballot resolution process, the ISAC needs to
discuss with you the proposed response to your negative comment. Your
comment was:

  All references to VHPI should be made optional - should be removed
  from body of the LRM into an Appendix.

And your proposed resolution was:

  Move VHPI to an Appendix - Annex and state that it is optional

The ISAC has considered your comment and proposes not to implement your
suggestion. The rationale is as follows:

The VHPI was incorporated into VHDL as an amendment, 1076c. Its inclusion as
an integral, non-optional part of the standard was approved by the balloting
body for the amendment project, and the amended standard was approved by
IEEE in 2007.

Specification of the VHPI requires some significant changes to details of
aspects of the language, notably, to the simulation cycle as specified in
Clause 12 of IEEE 1076c-2007. Making the VHPI optional would require
specifying and maintaining two versions of the simulation cycle, one without
VHPI and one with VHPI. This would be difficult and error prone.

The ISAC notes that a minimal implementation of the VHPI need not be
burdensome. The VHPI provides a means for a tool to provide a subset of the
full VHPI capability and for VHPI programs to query the capabilities
provided by the tool (see subclause 17.3 of D4.2). A minimal implementation
need only provide the function interface described in Clause 23 and Annex B,
with none of the capabilities described in 17.3 being implemented by the
tool. Calls to the functions would generally return an error indication.

I would be grateful if you would indicate whether this is acceptable to you
and whether, as a consequence, you would change your vote from Disapprove to
Approve. If not, would you like to offer any alternative proposal that the
ISAC could consider?

Once again, thank you for your participation. The ISAC very much appreciates
your longstanding involvement with the VHDL standard.

Best regards,

Peter Ashenden
P1076 Technical Editor

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Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
PO Box 640                    VoIP: sip://0871270078@sip.internode.on.net
Stirling, SA 5152             Phone: +61 8 7127 0078
Australia                     Mobile: +61 414 70 9106 


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