Subject: ITC Meeting Minutes
From: Bailey, Brian (brian_bailey@mentorg.com)
Date: Mon Nov 18 2002 - 10:40:48 PST
Please let me know of any errors, omissions or other corrections necessary in these minutes.
Thanks
Brian
Accellera ITC Technical Committee meeting
SCE-MI Sub-committee
November 15th 2002
Attendees
Richard Newell - Aptix
Farid Morsi - Aptix
Jason Andrews - Axis
Andrea Castelnuovo - ST
Andy Ellopoulous - Cadence
Jan Johnson - Mentor Graphics
John Stickley - Mentor Graphics
Brian Bailey - Mentor Graphics
Joe Daniels - Tech Writer
Agenda
Introduce Joe Daniels
Set Timeline for advancing document to Accellera board
Consider name change of the document
Set date of next face to face meeting
Outstanding issues in the document
Notes
Joe introduced himself and gave a list of his accomplishments in the preparation of documents for Accellera and IEEE standards. Joe is to be the tech writer that will take our current document and do the necessary reformatting work to bring it into line with Accellera and IEEE templates etc.
We will have a face to face meeting on December 3rd in San Jose. This corresponds to other Accellera events going on in the same timeframe. On Dec 4th there will be a whole day committee meeting on the combined SystemVerilog committees. On the 5th is a 1/2 day Accellera public tutorial session that will let people know the current state of the work inside of Accellera. We will plan for our meeting being a whole day event, but will curtail if we find that we have completed the work earlier.
At that meeting, Joe will have a partially restructured document to share with us. This may raise issues that need to be address in the meeting. Joe has also stated that he would have a version of the document with annotated open issues ready by the 2nd week of Jan. It is planned that a first draft of the complete document will be available by the end of January on which a formal vote of acceptance will be made and passed onto the board.
Issues
There appear to be no major issues with the document at this stage. Some items were brought up that may need more discussion to be fully resolved.
Status of document with respect to recent developments with SystemC and SystemVerilog.
This is not thought to be an issues, but will be explored before the Dec meeting
Acceptance test / Compliance test availability.
There is no intention of providing a complete compliance suite. Mentor has made available a binary reference version of the tutorial, which can be used as one test for compliance. However, it does do exercise the complete specification. We should encourage others in the group to donate working models and examples to help other people test their solutions. ** Does EVE have anything that could help here ?
Separation of document sections
The tutorial is normally not a part of a standards document. For Accellera standards we can leave it in as an appendix, but for the IEEE will have to be removed. We may need to put more explanation into section 2 and/or a forward reference to the appendix if chapters 1,2 and 4 are not self supporting.
VHDL support
Should this be provided?
Input Synchronization
A question was raised as to if it is possible for two transactors to be 'fired' in a synchronous manner. John S. explained that while there is no direct support, a policy for doing this can be build on top of the SCE-MI infrastructure.
Document Name - Accellera normally does not use commercial names for the standard. This raised the question of it SCE-API was a proprietary name and needed to be changed.
The name has never been used for any product and was conceived by the original consortium. There is thus no need to change it.
Issue Closed
==============================================
Brian Bailey brian_bailey@mentor.com
Chief Technologist Tel: 503 685 1371
System Verification Development Office Fax: 503 685 1652
Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070
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