Subject: RE: Synchronization with SystemVerilog 3.1A
From: Andy Eliopoulos (andye@cadence.com)
Date: Thu Jun 19 2003 - 09:00:49 PDT
Hi Vassilios,
It appears you may have misinterpreted the "tone" of my question. The
question was to the expansion of a language neutral technology like
SCE-API being part of any language specification. SCE-API should be
available from Verilog, SystemVerilog, VHDL, and SystemC. Especially
SystemC since it is already standardizing C++ interaction in the
hardware design world. Understanding the reason why SCE-API needs
further unification with SystemVerilog over the other languages.
Andy
> -----Original Message-----
> From: Vassilios.Gerousis@infineon.com
> [mailto:Vassilios.Gerousis@infineon.com]
> Sent: Wednesday, June 18, 2003 12:06 AM
> To: Andy Eliopoulos; brian_bailey@mentorg.com; itc@eda.org
> Cc: dennisb@model.com
> Subject: RE: Synchronization with SystemVerilog 3.1A
>
>
> Hi Andy,
> The issue is not SystemVerilog versus IEEE. Accellera
> is developing multiple standards which must be synchronized
> before we donate them to IEEE. As an Accellera organization,
> our different teams must collaborate together to develop
> cohesive standards that should interoperate between each others.
> Last year we did collaboration between SystemVerilog
> and PSL. This year, the Accellera organization would like to
> extend this to other standards based on technical chairs
> discussions on this matter. FYI, all chairs of Accellera are
> in one steering committee called TCC. Brian being the chair
> is part of this technical steering committee. TCC help to
> advise and collaborate.
> The tone of your email, indicate you do not want to
> collaborate between Accellera working groups. As a technical
> person, are you advocating that we do not work together?
>
> Vassilios
>
> -----Original Message-----
> From: Andy Eliopoulos [mailto:andye@cadence.com]
> Sent: Tuesday, June 17, 2003 8:37 PM
> To: Bailey, Brian; itc@eda.org
> Cc: Brophy, Dennis
> Subject: RE: Synchronization with SystemVerilog 3.1A
>
>
> Brian,
>
> Do we really need to go down the path of SystemVerilog
> v. IEEE Verilog 1364-2005, or should this committee
> continue to develop a neutral API?
>
> Andy Eliopoulos
> Cadence
>
>
> > -----Original Message-----
> > From: Bailey, Brian [mailto:brian_bailey@mentorg.com]
> > Sent: Tuesday, June 17, 2003 11:18 AM
> > To: 'itc@eda.org'
> > Cc: Brophy, Dennis
> > Subject: FW: Synchronization with SystemVerilog 3.1A
> >
> >
> > Hi Guys,
> > We have some marching order from our boss, that we have
> to look at
> > ensuring the SCE-API is compatible with SystemVerilog by February
> > 2004. That means that we have to get started on looking at what
> > problems we may have and the steps that we need to take.
> > Since I didn't hear any comments about my last posting,
> > or about the proposed date for the next meeting, then I will
> > set it to be: Thursday 26th June at 9:00 PST.
> >
> > Call in details
> > 888 742 8686
> > Intl 303 928 2600
> > Conf ID 4252566
> >
> > Agenda Items
> > Donation procedures and process
> > Workshop planning
> > SCE-API and SystemVerilog
> > Any other business
> >
> >
> > -----Original Message-----
> > From: Vassilios.Gerousis@infineon.com
> > [mailto:Vassilios.Gerousis@infineon.com]
> > Sent: Tuesday, June
> > 17, 2003 6:58 AM
> > To: srikanth.chandrasekaran@motorola.com; Bailey, Brian
> > Cc: david.smith@Synopsys.COM; fhaque@cisco.com;
> > Ghassan.Khoory@Synopsys.COM; Karen.Pieper@Synopsys.COM;
> > Stephen.Meier@Synopsys.COM; mittra@juno.com;
> > johny.srouji@intel.com; Ghassan.Khoory@Synopsys.COM
> > Subject: Synchronization with SystemVerilog 3.1A
> >
> >
> > As part of my announcement on SystemVerilog 3.1A (to be
> completed by
> > DVCON 2004), I have added synchronization with Verilog-AMS and also
> > SCE-API.
> >
> > We are proceeding on a set of milestones for
> > SystemVerilog. This includes support of synchronization of
> > the three standards. Without these synchronization we cannot
> > go to IEEE. Here what I expect at minimum:
> >
> > 1- Verilog-AMS should at least use the SystemVerilog 3.1 BNF (to be
> > modified for 3.1A). The BNF is available of SystemVerilog 3.1 is
> > available for use. This is based on IEEE 2001 Verilog.
> >
> > 2- Verilog-AMS could use some of the new data types like
> real, etc. It
> > could also examine the use of interfaces as
> > mechanism of adding an analog macro to a SystemVerilog. It
> > can also inherit some of the Testbench capabilities and
> > possibly assertions.
> >
> > 3- In terms of SCE-API, we talked about separating the
> current SCE-API
> > into three parts. One of them could be the C-interface
> defined for SV
> > 3.1. We can also start the emulation acceleration and see what that
> > can bring to both committees.
> >
> > Let me know what your thoughts are.
> >
> > Best Regards
> >
> > Vassilios
> >
> >
>
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