Subject: Re: When is Cycle Stamp 0?
From: Stickley, John (john_stickley@mentorg.com)
Date: Fri Feb 27 2004 - 08:19:31 PST
Per,
Right now we're starting it after ureset. Is there a
reason you can see to do otherwise ?
I do agree that we should be specific about this for
consistency among implementations.
-- johnS
Bojsen, Per wrote:
> Hi,
>
> while we are on the topic of cycle stamp I thought I'd
> throw this minor detail in there as well:
>
> When is the (implicit) cycle stamp counter 0? I think
> the SCE-MI standard has some language to the effec that
> the cycle stamp is the number of implicit 1/1 clock
> cycles since the beginning of emulation/simulation. But
> is this considered to be before creset is asserted, i.e.,
> literally when you switch the box on, sometime during creset,
> or just after creset is deasserted. Or is the cycle stamp
> counter reset by ureset?
>
> I was hoping that the SCE-MI standard would define cycle
> stamp such that an application would get the same cycle
> stamp values regardless of which implementation it is
> running on provided `sane' clock control is used, i.e.,
> cclocks are stopped during transfer of messages. Is this
> true?
>
> Per
>
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