RE: Minutes from meeting

From: Jason Andrews <jason_at_.....>
Date: Tue Mar 29 2005 - 15:24:31 PST
Hi Brian,

Here is our feedback on the goals. It comes from Jason Rothfuss
and myself.

Thanks.

-----------------------------------------------------------------

Verisity Feedback on SCE-MI 2.0 goals as outlined by Duaine on slides 11-15


1. Reference Implementation and Compliance Suite
---------------------------------------------------
Our most important feedback is the goal of the committee to provide a
reference 
implementation of SCE-MI and a test suite to help ensure compliance by all
vendors.
We feel this is the best way to achieve the goals of enlarging the market
for EDA 
vendors and enabling increased development of VIP by users and 3rd parties.

A free implementation that runs on all popular simulators is a must to
spread SCE-MI 
to a wider audience. The reference may or may not include source code, but
it must run
easily on popular platforms. We don't have complete approval at this time,
but we
would be interested to provide this. 

We feel the goal of SCE-MI is to enable a large set of models for users that
run the
same way on all acceleration/emulation/prototyping systems. This allows
users to 
choose products based on the features and benefits vs. choosing based on
available models. 
If this is not the goal then we should all go back to proprietary interfaces
and selling 
models that only work on our own platforms.

2. Ease-of-Use
--------------
We support any activities to make the life of the model developer easier.
Enhancements 
to simplify clocking, the use of variable length messages, and data
streaming are examples. 
This supports of the goal of not requiring A+ engineers to develop models.
By providing the 
reference environment discussed in #1 more engineers can learn how to
develop models.

3. Languages
-------------
We support continued use of C/C++
Every other language used in verification can easily call and be called by
C.

4. Acceleration Subset
----------------------
We do NOT support any effort to define a new subset of Verilog, VHDL, or
System Verilog 
for the purposes of accelerating modeling constructs.
We feel the current de facto standards are sufficient for engineers to
develop models. 
As new enhancements to the current languages used for design are made they
can be 
adopted for modeling. SCE-MI is an interface and not about developing
special synthesis 
tools for acceleration. Even though we develop such tools in Verisity (such
as e synthesis) 
we don't see this as useful for improving the standard and promoting
increased usage. 
In fact, it would likely lead to vendor separation based on proprietary
synthesis tools 
and make interoperability even worse than it is now.



> -----Original Message-----
> From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf 
> Of Brian Bailey
> Sent: Thursday, March 24, 2005 10:59 AM
> To: itc@eda.org
> Subject: Minutes from meeting
> 
>         Please find attached the minutes from today's 
> meeting. Important action item for everyone - all proposed 
> modification, or acceptance of the goals must be mailed to me by 3/30
>         
>         Thanks
>         Brian 
> 
Received on Tue Mar 29 15:24:34 2005

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