Hey, quick question about clock phase control in the SceMiClockPort macro. What does the spec say or infer about phase resolution? In other words, if one were to specify some phase (say 47,53) that makes so sense for that controlled clock (say, one that is 4x the period of the fastest controlled clock), what should happen? Is the phase rounded up or down (to 50,50 or 25,75 for this example)? --------------------------------------- --- Russ Vreeland (949)926-6143 --- --- vreeland@broadcom.com --- --- Senior Principal Engineer --- --- Broadcom Corporation --- ---------------------------------------Received on Wed Jun 8 16:03:22 2005
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