Re: SCEMI 1.1 question

Hi Russ,

> Hey, quick question about clock phase control in the SceMiClockPort
> macro.
> 
> What does the spec say or infer about phase resolution? In other words,
> if
> one were to specify some phase (say 47,53) that makes so sense for that
> controlled clock (say, one that is 4x the period of the fastest
> controlled
> clock), what should happen? Is the phase rounded up or down (to 50,50 or
> 25,75 for this example)?

Given that the spec says nothing about rounding, a compliant
implementation is required to realize the phase as specified by
the user.  I believe what matters is that the rules about clock
edges and their ordering between clocks (controlled and uncontrolled)
are followed.  So if you had two controlled clocks in your testbench,
one with phase 47/53 and the other with 50/50, and of the same period
with the same phase shift, then the falling edges of these two clocks
should never occur coincident with the same rising edge of uclock.
Their rising edges, however, should occur coincident with the *same*
rising edge of uclock.  So you should see rising edge of both clocks,
falling edge of the 47/53 clock, falling edge of the 50/50 clock,
all coincident with different uclock rising edges in that order.

It is a different question whether the 47/53 clock would actually
look like a 47/53 clock if you put your scope to it.  I believe
the spec does not require this.  It is only concerned about clock
edge ordering.

Per