> Action Item: Before the next meeting, everyone should send to > the reflector the SOLUTION that they would like to see for the Verilog > datatype coercion issue. Zaiq would prefer to see old Verilog supported with the attribute style a long the lines of John's strawman proposal. This allows models to be written in old Verilog in a way that is syntactically correct. Further we would like for such models/transactors to be acceptable to a SCE-MI 2.0 infrastructure linker that is running in SystemVerilog mode as well. This allows users to use old Verilog transactors and fragments of such without having to rewrite the code (with the exception of the keyword issues Shabtay brought up, of course). The attribute style function declarations are also valid SystemVerilog so should be accepted in the SystemVerilog mode of SCE-MI as well. Furthermore, this will allow the full complement of attributed types to be supported in Verilog as proposed by John as the attribute style of SCE-MI function call would continue to work when moved to SystemVerilog. Of course, this would not be automatically accepted by a SystemVerilog simulator but neither would it be by a Verilog simulator. The infrastructure linking step is required before simulation can proceed. As an aside, I believe regarding VHDL I believe we should add std_ulogic and std_ulogic_vector types which can be trivially supported, but also the two-state BIT and BIT_VECTOR types. As an interesting observation, we're fretting over whether to map old Verilog's 4-state bit vector types to two state types on the C side, yet on the VHDL side we have accepted to map the 9-state bit types to two state types without any discussion :-) Note, I agree with this, as multi-state logic types are not that useful in emulation. Per -- Per Bojsen Email: <bojsen@zaiqtech.com> Zaiq Technologies, Inc. WWW: http://www.zaiqtech.com 78 Dragon Ct. Tel: 781 721 8229 Woburn, MA 01801 Fax: 781 932 7488Received on Thu Aug 25 14:25:21 2005
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