SCE-MI 2.0 HDL Support (Re: Meeting minutes 050825)

Hi,

I've previously commented on Zaiq's opinions on the support for `old'
Verilog in SCE-MI 2.0.  Shabtay (Cadence) and Russ (Broadcom) also
commented on VHDL.

Zaiq supports the principle that the choice of HDL should be
transparent to the software side, i.e., the user should be able
to use `old' Verilog, SystemVerilog, and VHDL interchangeably
without having to rewrite the software side.  This implies that
all three languages should have support for a function based
interface based on SystemVerilog DPI.  It also means, that if
we decide to add the new macros Cadence is proposing they should
be available in all three languages.  A hybrid approach where
VHDL only has macro support and SystemVerilog and `old' Verilog
only has the function based interface would lead to a HDL
dependent use model that would probably lead to IP vendors avoiding
support for SCE-MI at worst or dropping support for VHDL at best.

When considering how HDLs are handled in SCE-MI it is important to
observe that the HDL portion of a SCE-MI application is not seen
directly by a simulator or synthesis tool.  It is processed by the
infrastructure linker first.  With the introduction of support of
SystemVerilog DPI we are trying to create a situation where the
it is possible to run the SCE-MI application in a SystemVerilog
simulator without requiring the infrastructure linker as long as
the SCE-MI application is written within the strict DPI subset of
SCE-MI 2.0.  However, for `old' Verilog, VHDL, and SystemVerilog
where more than the DPI subset of SCE-MI 2.0 is used, the
infrastructure linker is required.

Having said that, Zaiq believes there are pragmatic reasons that
the SCE-MI 2.0 function interface extensions to `old' Verilog
and VHDL should be expressable entirely within the legal syntax
of those languages.  Theoretically we are not restricted to legal
syntax since the infrastructure linker could parse any syntax
extensions we care to define and still ensure the output is
acceptable to whatever synthesis tools and/or compilers will run
after the linking phase.  But if we restrict ourselves to legal
syntax implementors have more choice in terms of available
third-party language parsers, etc.  So this is purely a pragmatic
consideration.  John Stickley has pointed out several times that
his proposals follow the legal syntax of each language so this
issue should be easy to settle.  Shabtay's objection to supporting
the function based interface in VHDL seemed to be rooted in this
issue as well.  So hopefully we can come to an agreement quickly.

Thanks,
Per

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
78 Dragon Ct.                             Tel:   781 721 8229
Woburn, MA 01801                          Fax:   781 932 7488