RE: HDL Support (was RE: Meeting minutes 050825)

Russ, Brian,

Addressing both comments in a single email, I definitely have seen
customers viewing the compliance from their language domain perspective
and (similar to you Russ) never bothered to ask if the implementing
supports languages that they don't use. However they have not looked at
it from the same language that you looked at SCE-MI 1.1(Verilog). This
is as far as I can go on this.

I agree with Brian that vendors could claim compliance with a subset of
SCE-MI 2.0 and state the languages/areas that they are not compliant
with. SCE-MI 2.0 spec should not be defined to support only one/few of
the languages.

Shabtay


>-----Original Message-----
>From: Brian Bailey [mailto:brian_bailey@acm.org]
>Sent: Thursday, September 15, 2005 3:15 PM
>To: Shabtay Matalon; bojsen@zaiqtech.com
>Cc: vreeland@broadcom.com; 'John Stickley'; itc@eda.org
>Subject: RE: HDL Support (was RE: Meeting minutes 050825)
>
>I do not think we ever stated that everything was needed for a
compliant
>implementation, but in general I believe that the industry states that
if
>it
>is written in a definitive part of a standards document, then if it is
not
>all supported then it is a subset implementation. The standard is the
>definitive part of the document and in that part the Verilog and VHDL
>wrappers are defined as well as the C and C++ bindings. I thus think it
>fair
>to say that a fully compliant implementation should support all 4
languages.
>
>However, I think Russ has a point, that there are useful subsets, and
we
>should not preclude those subsets so long as the vendor makes it very
clear
>that they have delivered a subset. In the past, it has then been
customer
>pressure and adoption that has led standards group to deprecate certain
>aspects of a specification.
>
>Just my views on the matter.
>Brian
--------------------------------------------------------

>-----Original Message-----
>From: Russell Vreeland [mailto:vreeland@broadcom.com]
>Sent: Thursday, September 15, 2005 2:56 PM
>To: Shabtay Matalon; bojsen@zaiqtech.com
>Cc: 'John Stickley'; itc@eda.org
>Subject: RE: HDL Support (was RE: Meeting minutes 050825)
>
>Just curious, did SCEMI 1.1 compliance mandate supporting both
>VHDL and Verilog?  As a user who's tested several different
>SCEMI 1.1 products, I never bothered to ask if they had VHDL
>support since we are almost exclusively a Verilog house. It
>wouldn't occur to me to protest if I was marketed a product
>that was "SCEMI 1.1 compliant, verilog only" (or VHDL only
>if we were a VHDL house). Same goes for SCEMI 2.0.
>
>I'm not trying to advocate anything here, just a user's perspective.
>
>---------------------------------------
>---    Russ Vreeland (949)926-6143  ---
>---    vreeland@broadcom.com        ---
>---    Senior Principal Engineer    ---
>---    Broadcom Corporation         ---
>---------------------------------------
>
>
>
>> -----Original Message-----
>> From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf
>> Of Shabtay Matalon
>> Sent: Thursday, September 15, 2005 2:23 PM
>> To: bojsen@zaiqtech.com
>> Cc: vreeland@broadcom.com; John Stickley; itc@eda.org
>> Subject: RE: HDL Support (was RE: Meeting minutes 050825)
>>
>>
>> Per,
>>
>> SCE-MI 2.0 compliance should mean supporting all the 3
>> languages (SystemVerilog, VHDL or Verilog 2001). We should
>> not support the concept of building SCE-MI 2.0 as
>> SystemVerilog only standard or define SCE-MI 2.0 compliance
>> in the domain of only one language (SystemVerilog for example).
>>
>> This should not preclude us from working the issues in each
>> language a step at a time. We can address each issue for the
>> 3 language at the same time or work one language at a time
>> and reconcile as deems logical to us as a group.
>>
>> I will not get into C vs. C++ at this time as this may need
>> more thought and discussion.
>>
>> Shabtay
>>
>> >-----Original Message-----
>> >From: Per Bojsen [mailto:bojsen@zaiqtech.com]
>> >Sent: Thursday, September 15, 2005 1:30 PM
>> >To: Shabtay Matalon
>> >Cc: vreeland@broadcom.com; John Stickley; itc@eda.org
>> >Subject: HDL Support (was RE: Meeting minutes 050825)
>> >
>> >> We at Cadence believe that the decision which language to
>> use for DUT
>> >> and BFM modeling (SystemVerilog, VHDL or Verilog 2001)
>> should be made
>> by
>> >> our customers and that a SCE-MI 2.0 standard should respect this
>> >> assumption and provide a solution that does not compromise
>> the needs
>> of
>> >> any of the SystemVerilog, Verilog 2001 and the VHDL communities.
>> >
>> >This leads to the following question: For a SCE-MI
>> implementation to be
>> >considered compliant must it support all languages supported by the
>> >standard, or is there a concept of a compliant SystemVerilog
>> >implementation, etc.? This of course also extends to C versus C++
>> >support.
>> >
>> >Per
>> >
>> >--
>> >Per Bojsen                                Email:
>> <bojsen@zaiqtech.com>
>> >Zaiq Technologies, Inc.                   WWW:
>> http://www.zaiqtech.com
>> >78 Dragon Ct.                             Tel:   781 721 8229
>> >Woburn, MA 01801                          Fax:   781 932 7488
>> >
>> >
>>
>>
>>
>
>