RE: supporting DPI in VHDL - possible scenarios for implementation

I'll defer to the simulation vendors to speak expertly on relative levels of
difficulty.

My bottom line is that a small filtering process on the HDL side is not
onerous -- especially given that the supposedly less onerous library-only
solution is in practice one that is just as proprietary and non-portable as
using a small IFLC-like front-end prior to simulation. A requirement that
two entirely different paradigms on the C side be supported for one model
seems much more unreasonable.

---------------------------------------
---    Russ Vreeland (949)926-6143  ---
---    vreeland@broadcom.com        ---
---    Senior Principal Engineer    ---
---    Broadcom Corporation         ---
---------------------------------------



> -----Original Message-----
> From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf 
> Of John Stickley
> Sent: Tuesday, October 04, 2005 12:44 PM
> To: vreeland@broadcom.com
> Cc: Shabtay Matalon; itc@eda.org
> Subject: Re: supporting DPI in VHDL - possible scenarios for 
> implementation
> 
> 
> Russ,
> 
> One additional thing I would add to one of your points
> in here:
> 
> Russell Vreeland wrote:
> > This would be
> > a harder problem -- converting a function call to a structural 
> > implementation is beyond a one-pass perl script -- but shouldn't be 
> > difficult for a major-league simulation vendor. The 
> advantage would be 
> 
> johnS:
> I would venture to say that even creating a structural 
> implementation would not ever be necessary in a S/W 
> simulator. Only when going to an emulator that takes a 
> synthesized gate level representation might this become 
> necessary. But in that case, infrastructure synthesis was 
> already a requirement for SCE-MI I and this does not really 
> add much to that requirement.
> 
> > 
> > ---------------------------------------
> > ---    Russ Vreeland (949)926-6143  ---
> > ---    vreeland@broadcom.com <mailto:vreeland@broadcom.com> 
>        ---
> > ---    Senior Principal Engineer    ---
> > ---    Broadcom Corporation         ---
> > ---------------------------------------
> 
> -- johnS
> 
> ______________________________/\/            \     \
> John Stickley                   \             \     \
> Mgr., Acceleration Methodologies \             \________________
> Mentor Graphics - MED             \_
> ________________________________________________________________
>