4 State support proposal

Dear Colleagues:

We would propose that 4 state be supported in the SCE-MI 2.0
Interface.

Four valued System Verilog data types, reg, logic, and integer should
be treated as four valued at the DPI interface.

The C side mapping would be to svLogic, svLogicVec32,
svLogicPackedArrRef.

e.g.,

/* (a chunk of) packed logic array */

typedef struct { unsigned int c; unsigned int d;} svLogicVec32;

The encoding would follow the SV definition:

c	d	Value

0	0	0
0	1	1
1	0	z
1	1	x

[the above is the same as "old" Verilog's aval/bval encoding]

The implementor has the choice of
	a) coercing to two state by dropping 'c'
	b) warning and coercing
	c) generate error and stop; the error can be at compile time
	   if an implementation disallows reg, logic, and integer in
	   the relevant function interface.

Most synthesis and emulation platforms accept reg, integer and coerce
to two state. The proposed approach for SCE-MI is consistent with that
approach.

If desired VHDL subtype X01Z can be supported with the same encoding
as SV logic/reg.

-- 
regards,
Ramesh