SystemVerilog 4-state logic value support proposal

Hi,

there are only to reasonable ways we can go on the 4-state logic
value issue:

1) Only 2-state logic value types are supported.  Any use of 4-state
   logic types or any other types not supported by the SCE-MI DPI
   subset is an error.

2) 4-state logic value types are supported in the following limited
   sense: 0 and 1 values are passed in either direction on changed;
   any attempt to pass X or Z in either direction is an error.  4-state
   logic values are not coerced to 2-state logic values.

It should be pretty straightforward to define the SystemVerilog types
such that most of the above error cases become compile time errors on
the C side.  Since the infrastructure linker does not process the
C side it is not the infrastructure linker's job to report these
errors.

Per