RE: supporting DPI in VHDL - possible scenarios for implementation

 
comments embedded
-----Original Message-----
From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf Of Shabtay
Matalon
Sent: Tuesday, October 04, 2005 6:14 PM
To: vreeland@broadcom.com
Cc: John Stickley; itc@eda.org
Subject: RE: supporting DPI in VHDL - possible scenarios for implementation



Russ,

 

My proposal to John to illustrate using Verilog 2001 the proposed
function-based approach for simulation focuses the discussion. I am truly
hoping that John will pick this up and share the results with us so we can
move forward on this crucial point. 

 

John spent a lot of time illustrating the function-based approach for
VHDL.... What is so different about Verilog 2001? There are only two cases:
simulators that support DPI, and those that don't but do support function
calls + attributes -OR- structural instantiations.

 

I suspect it was a mistake to try to resolve this issue at this time. The
other issues which are pertinent to the SystemVerilog case ought to

be tackled first, then we can come back to VHDL and Verilog2001. The great
technical advancement of SCEMI 2.0 is (using SystemVerilog) we can achieve a
testbench methodology truly portable from simulation to emulation. We should
solve remaining SystemVerilog issues without distraction. Then, this optimal
solution will help us figure out the (necessarily) less optimal solution for
the other simulators. 

 

What does the rest of the committee think? Is it time to table this issue
lest we spend the rest of the time available for technical discussions on
it? Perhaps given the time constraints, this is a SCEMI 2.1 issue.

 

You rephrased some of the points in my email in a way that I disagree with.
In particular you implied that we proposed a SystemVerilog only SCE-MI 2.0
standard. 

 

Huh? ??????????????????  No one thinks Cadence proposes a SystemVerilog only
standard.

 

We also have been holding on officially bringing our macro based proposal
now to the committee in spite of the fact that these macros meet all
principles stated across the three HDLs with the only exception that these
are not function-based on the HW side. We also stated our support for SCE-MI
2.0 to be DPI-based standard for SystemVerilog. 

 

The one principle that they do not meet is the furtherance of  portable IP
written for both simulation and emulation. Also, if you say you support

SCEMI2.0 to be DPI-based for SystemVerilog, then why state that the macros
meet all principles for SystemVerilog (one of the 3 HDLs).?

 

Thanks,

 

Shabtay

 

Cordially,
Russ

---------------------------------------
---    Russ Vreeland (949)926-6143  ---
---     <mailto:vreeland@broadcom.com> vreeland@broadcom.com        ---
---    Senior Principal Engineer    ---
---    Broadcom Corporation         ---
---------------------------------------