RE: supporting DPI in VHDL - possible scenarios for implementation

Hi Russ,

> What does the rest of the committee think? Is it time to table this
> issue lest we spend the rest of the time available for technical
> discussions on it?

I don't have a problem focusing on SystemVerilog for the time being
as long as we have a common understanding that everything we spec for
SystemVerilog carries over to regular Verilog and VHDL assuming we
will agree to adopt the function based interface for those languages
in the end.

>  Perhaps given the time constraints, this is a SCEMI 2.1 issue.

Are you suggesting we drop regular Verilog and VHDL support of the
new 2.0 features until 2.1?  In other words, leave SCE-MI at 1.1
for Verilog an VHDL and only include the new features for
SystemVerilog?  Perhaps not quite as drastic, if we focus on nailing
down the SystemVerilog support vendors can come out with a pre-2.0
SCE-MI implementation that supports SystemVerilog sooner allowing
customers to try it out before the standard is actually finalized.
This is not unheard of.  Take C++ for instance: there were plenty
of C++ compilers out there years before C++ became a standard.

Per