Hi John, > I'm OK with tabling the discussion as long as we don't > drop consistent function call support for all three languages > from the SCE-MI 2.0 agenda. > [...] > But given the concensus we've reached on this, dropping > it from the 2.0 agenda would, in my view, be a big > mistake. I agree with you here. I don't mind focusing on SystemVerilog for a while, except I'd like to make sure we do not end up defining something that would be incompatible with VHDL and `old' Verilog. I also agree that it would be a mistake to drop 2.0 support for `old' Verilog and VHDL. We were very close on agreeing upon the syntactical issues that would have allowed us to deal with the rest of the issues in a language neutral way. As a compromise I propose that we move along nailing down the SystemVerilog portion of SCE-MI 2.0 to the point where vendors can start implementing. Then we can return to VHDL and Verilog and finalize SCE-MI 2.0 with VHDL and Verilog support. PerReceived on Wed Oct 12 21:13:12 2005
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