Hi Brian, > If we completely deadlock on the VHDL/Verilog issues, then we should > push forward with a limited standard that covers the 2 languages only, Didn't you mean the *one* language only, i.e., SystemVerilog? > but make sure we provide a clear timetable of when the other languages > will be supported directly, rather than being left on the 1.X > standard. We should also state some hints as to what we intend to do with those languages. PerReceived on Wed Oct 12 21:16:57 2005
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