Re: Transaction Pipes deadlock scenario?

Jason,

Sorry about the delayed response here.

This problem is solved by making sure the C side infrastruction
is given the same opportunity at initialization as initial blocks
which, generally on a mixed mode simulator (such as
SystemC/VHDL/Verilog) it should.

If the pipe is written to by the C side in 0-time, no deadlock
will occur. If the pipe is written to at some time > 0,
yes this is a user-induced deadlock which is indeed
possible just as many user-induced deadlocks are
possible within pure Verilog itself.

The following is an example of a user-induced deadlock
in pure Verilog that is somewhat comparable to the
pipe scenario you described:

event e;
reg clock;

initial begin
     clock = 0;
     @e;
     forever #(`half_period) clock = ~clock;
end

initial begin
     @(posedge clock);
     -> e;
end

So to answer your question, are user-induced deadlocks
possible with pipes ?

Yes. But they generally are easily avoidable if starved or
full pipes are responded to in 0-time as is typical for
untimed testbenches.

-- johnS

Jason Rothfuss wrote:
> What should happen in this case:
> 
>  
> 
> Consider the following environment:
> 
>  
> 
> *_Software Side_*
> 
> 	
> 
> *_ _*
> 
> 	
> 
> *_Hardware Side_*
> 
> Producer A
> 
> 	
> 
>> >> Pipe A >>>
> 
> 	
> 
> Consumer A
> 
>  
> 
> Let's say you do:
> 
>  
> 
> initial begin
> 
>    dpi_pipe_hdl_receive( <Pipe_A> ); 
> 
> end
> 
>  
> 
> By doing this, haven't we created deadlock?  Simulation time cannot 
> advance because the consumer of Pipe A cannot be starved.  Also, Pipe A 
> does not know who it's producer is at this point, so it cannot yield to 
> the producer.  If this is all true, perhaps you can't call receive on 
> the HDL side before calling send on the SW side?
> 
>  
> 
> Regards,
> 
> Jason
> 
>  
> 
>  
> 
> *Jason Rothfuss*
> /Cadence Verification Division/
> 
> 
> *Cadence Design Systems, Inc.*
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