Hi John, I've been thinking about Transaction Pipes some more, and I'm wondering what should happen in this case: Consider the following environment: Software Side Hardware Side Producer A >>> Pipe A >>> Consumer A Let's say you do: initial begin dpi_pipe_hdl_receive( <Pipe_A> ); end By doing this, haven't we created deadlock? Simulation time cannot advance because the consumer of Pipe A cannot be starved. Also, Pipe A does not know who it's producer is at this point, so it cannot yield to the producer. If this is all true, perhaps you can't call receive on the HDL side before calling send on the SW side? Regards, Jason Jason Rothfuss Cadence Verification Division Cadence Design Systems, Inc. 16279 Laguna Canyon Road Irvine, CA 92618 Office: +1 (949) 790-7181 Mobile: +1 (310) 210-2754 rothfuss@cadence.com www.cadence.com C a d e n c e <http://www.cadence.com>Received on Fri Dec 23 16:14:24 2005
This archive was generated by hypermail 2.1.8 : Fri Dec 23 2005 - 16:14:59 PST