Question about negedge active don't care duty cycle clocks and phase

Hi,

I'm sorry to have to do divert the attention from the SCE-MI 2.0
discussions, but one of our customers brought up an interesting point.
It concerns negedge active don't care duty cycle clocks and the phase
setting.  The 1.1.0 spec states on p. 30 in the section with the
heading `DutyHi=0, DutyLo=100, Phase=0' that the phase setting
determines how much the clock is shifted `before the first low to
high transition occurs'.  In other words, the phase setting controls
when the posedge of the clock occurs.  However, for a negedge
active don't care duty cycle clock, that would seem to lead to a
contradiction: for such a clock we do not care where the posedge
lies.  Say Phase is set to 0.  This would force the posedge to occur
at the point of alignment if the quote above is to be believed.

For negedge active clocks, the implementation is allowed to schedule
the posedge anywhere within the clock period.  But the requirement
quoted above fixes the location of the posedge relative to the
point of alignment.  Hence, the negedge location now becomes
implementation dependent even though one would expect the opposite.
Do you see the apparent contradiction?

Also, how can the quote above be consistent with figure 15 which
shows a 1/1 negedge active clock with its posedge aligned with a
falling edge of uclock?

I am hoping (perhaps in vain) there is a quick answer to this one.
But I'm thinking we at least have to rephrase the quote above.

Thanks,
Per

P.S.: It is Wednesday and I have not seen any discussion on the
pipes.  Does Cadence not have anything to say in reply to John's
email?  If yes, does this mean that all open issues have been
settled?

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
78 Dragon Ct.                             Tel:   781 721 8229
Woburn, MA 01801                          Fax:   781 932 7488