Follow-up > ^ Issue
LRM: 8.9 Driver-receiver segregation
The use of the hierarchy to split nets into seperate digital segments assumes that modules are either digital or analog. While this may be a reasonable restriction for the time being, it is probably a restriction that will be lifted at a later date as it precludes useful constructs (e.g. self checking A/D convertors). It also implies that swapping a mid-level module from analog to digital (or vice versa) changes the relationship for signals shared by same-domain parents and grand-children - which is undesirable.
Also, as each (digital) module that has a receiving process may have a different discipline and hence a different A2D convertor using the hierarchy deliberately as a segregation mechanism is redundant.
Note: the reason that disciplines are attached to port declarations is for consistency with other Verilog declaration mechanisms, the discipline should really be attached to the view of the port used by individual processes (currently an unsupported syntax). Ports are merely a mechanism for connecting processes (component models), and D/A conversion is required at the process boundary not the (hierarchical) port. I.e. (ideally) different processes within the same module should be able use different disciplines for their view of a port, and what we currently have is a syntax that handles the degenrate case of all processes viewing the signal the same way (and merged in the case of a digital module). As users are currently limited to one analog process in a module there is no need to make the distinction in Verilog-A modules, similarly the use of a 'reg' declaration in a digital module implies that all processes in that module share the driver (and receiver?) for that signal.