- + Issue 2: Driver-receiver Segregation

[Kevin Cameron, 01 Dec 2000]

Follow-up >

  Connect statements and the insertion of A/D & D/A 
  convertors is actually an extended form of 'signal 
  resolution' - both VHDL and Verilog have mechanisms 
  where all drivers of a signal have their values 
  merged and the result appears as the value for that 
  signal everywhere. The driver-receiver segregation 
  section in the Verilog-AMS LRM as it stands appears 
  inconsistent with this accepted approach and should 
  be restated. 
  
  [ In general for a net that appears in multiple 
  domains, the drivers in those domains need to be 
  converted to the domain of highest accuracy, 
  resolution is performed in the domain of highest 
  accuracy (analog) and the result converted back 
  to the lower accuracy domains. ]