- + Issue 7: Back-Annotation
[Kevin Cameron, 22 Dec 2000]
Follow-up >
Requirements
Compatibility
Verilog-AMS is expected to be a superset of Verilog. Verilog
uses SDF for back-annotation, which is a methodology that
does not require re-netlisting. For full compatibility Verilog-A[MS]
also needs a mechanism that supports back-annotation without
re-netlististing.
Methodology
Top-down/bottom-up design usually involves designing functional
blocks (modules) and then connecting them together to create
larger functional blocks initially without interconnect. Those
designs are then pushed through "place & route" to produce a
"physical" design. The design after P & R has the same hierarchy
as before, but the port connections are no longer simple connections
but wires on Silicon.
The working assumption with SDF was that wires can be treated as mostly
capacitive - which was mostly true when it was invented. In "deep-submicron"
circuits wiring is relatively much longer and suffers from relatively
higher resistance and more crosstalk. A mechanism is required to back-annotate
the actual circuit of the wiring between the modules to model it accurately.
Proposal
The combination of the above requirements implies Verilog-AMS requires a
mechanism to disconnect the ports of a module from their hierarchical
parent and reconnect them into the extracted wiring model. There are
two ways we may want to do this:
- PLI
- Extended Language Syntax & Semantics
A PLI mechanism allows access to alien representations like SPF, and the
languge extensions allow re-use of Verilog-A[MS] descriptions (which is more
desirable long term).
Other requirements for the mechanism are that it should interoperate with
SDF and that it should be "exportable" - i.e. a back-annotated design should
be exportable for re-use in another design.