- + Issue 6: External Module Definitions

[Kevin Cameron, 22 Dec 2000]


Requirement

Verilog-A[MS] is intended to replace the use of SPICE netlists. In the initial cut of the language the approach was taken that models (primitive analog modules) were implicit and that any modules used in a Verilog-A description that were not declared would be found in the simulator.

This 'implicit declaration' approach has the problem that a design tool other than the actual simulator cannot tell if a design is complete. Modules which are required by a design but only supplied by a simulator need to be declared 'external' (as routines in C program modules are).

Proposal

I propose extending the Verilog-A syntax by allowing the keyword 'extern' before a module declaration, and that such a module declaration can only contain port, parameter and variable declarations (i.e. no processes).

I would also like to propose that the file including the standard (SPICE?) definitions is placed with the other simulation system include files accessible with: 

  `include <models.h>
Failure to locate a module definition would not be considered an error (but may cause a warning to be issued).

The information about the class of the module and the supporting simulators should be handled by a standard attribute mechanism.

NB:This mechanism may be extended later to handle cross-language issues.