- + Issue 17: Filters for foreign languages

[Kevin Cameron, 22 Feb 2001]


^ Issue

Addenda

The "extern" module syntax was (partially) intended for use with a lazy inclusion algorithm - i.e. if you don't see the module instaniated you don't run the filter. The filter should produce Verilog-AMS that can be parsed and added to the end of the previous input.

Since that might not suit some parsing schemes an unconditional inclusion syntax (with no module reference) is given below.

Note: Verilog 2000 has "`line" directives like the C pre-processor for identifying original source.

[Alternative] Proposal

For pre-processing only we could use: 

   `filter
	source   = <souce path>;
	language = <name string>;
        filter   = <program and arguments>;
	<extra text for filter input>
   `endfilter