- + Issue 938: (35) Annex E2: Case sensitive SPICE simulators

[Jon Sanders, 1/22/2001]

  (35) Annex E2: Case sensitive SPICE simulators
  
   Some spice simulators are case-sensitive, this should be accounted for too. Issues exists with the case-insensitive matching
   of SPICE components. Verilog is a case-sensitive language and if I write a Verilog construct (in this case an instantiation),
   it should comply with with the rules of Verilog i.e. case insensitivity. Believe it is better and more consistent with Verilog
   if all SPICE references must be lower-case, then the binding algorithm is much less complex.
   Consider that if I define a model called `Cap' and a module called `cap'. However if I type `cap' and expect to get `Cap', I
   would be wrong.
     Recommendation: Require all SPICE references to be lower case.