Subject: More Issues
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Dec 22 2000 - 11:54:17 PST
I added a couple more issues to the list: external
module definitions, and back-annotation.
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/
My notes from the last meeting say there is an issue with
the semantics for "cross module references" (was UMRs -
but I can't remember what the U is for), and it is related
to back-annotation in that it should be possible to add
components like coupling capacitors between children in
parent modules using UMRs - so we might want to consider
the two issues together.
Kev.
-- mailto:Kevin.Cameron@nsc.com
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