Subject: Re: More Issues
From: Jonathan Sanders (jons@cadence.com)
Date: Sun Jan 07 2001 - 23:23:26 PST
Kevin,
It should be OOMR (Out Of Module Reference). This issue mentioned
I believe is separate from the parasitic issue and has to do with the
discipline resolution method (to be included in my list). The impact of
OOMRs on other areas may need to be validated although I think we
will likely point out most of them.
As for using OOMRs for parasitic coupling capacitors and capacitors to
ground this is doable today using standard out of the box Verilog syntax.
In fact, I believe several of the fastmos SPICE like simulators do a similar
thing.
capacitor #(.c(1pf)) cp_top_i1 (top.i1.neta, gnd);
capacitor #(.c(0.1pf)) cp_top_i1 (top.i1.neta, top.i1.netb);
Jon
At 11:54 AM 12/22/00, Kevin Cameron x3251 wrote:
>I added a couple more issues to the list: external
>module definitions, and back-annotation.
>
>http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/
>
>My notes from the last meeting say there is an issue with
>the semantics for "cross module references" (was UMRs -
>but I can't remember what the U is for), and it is related
>to back-annotation in that it should be possible to add
>components like coupling capacitors between children in
>parent modules using UMRs - so we might want to consider
>the two issues together.
>
>Kev.
>--
>mailto:Kevin.Cameron@nsc.com
***********************************************************
Jonathan L. Sanders
Product Engineering Director
Mixed Signal and Physical Verification Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7265
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