Subject: Re: [D]SPF for back-annotation?
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 05 2001 - 10:29:24 PST
> From pragc@www.tdl.com Sun Feb 4 20:51:18 2001
>
> Correct me if I am wrong, but my impression is that analog models such
> as bsim 2 annotation is mostly through parameters. SDF can annotate to
> any AMS HDL object such as parameters, bodies (gates, instances, transistors),
> declarations, analog contribute statements, branches, etc. I do not
> understand how say cross talk is represented in Verilog-AMS. SDF is intended
> for post delay calculator values except non actual delay parameters can be
> annotated too - usually because the Verilog model does computation say computes
> loading formulas before using final value as a procedcural (usually) delay.
> Digital models are more and more moving to some delay calculation performed
> by HDL from annoatated to values.
>
> Currently, when new constructs are added to Verilog HDL, new SDF forms
> are added to SDF.
> /Steve
The problem with analog parasitics (for back annotation, usually from circuit
extraction) is that they need to be inserted into the un-annotated simulation
netlist in a way that does not disturb the name space. E.g. in an MS design
I would take some circuit described as cells (hierarchically) and run it through
"place and route" to get a "physical" design, my original circuit is still there
but the port connections which where previously assumed direct are now indirect
through the channel wiring, I may also have over-cell routing which introduces
extra cross-talk and parasitics within the cells too, and extra capacitive
coupling between the cells.
Verilog was originally designed when gate capacitance was the dominant value
in circuit timing, so SDF (which just modifies delay times) worked adequately.
Wiring is now dominant, so SDF isn't up to the job as the time to propagate
from a driver to a receiver can vary considerably between receivers.
So (ideally) I would like a design flow where I can take a mixed analog & digital
cell-based design (where I have accurate behavioral models) run it through P & R
and back-annotate at the level of SPF (Spice components), A/D convertors would be
inserted automatically for digital cells (that might have SDF back-annotation),
and I can then run my original test-bench (including probing the hierarchy) without
changes.
Kev.
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