Subject: Re: Overriding localparam value Issues
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 05 2001 - 10:02:33 PST
> From: "Srikanth Chandrasekaran" <schandra@asc.corp.mot.com>
> Subject: Overriding localparam value Issues
>
> Hi all,
> This is regarding the feature "local parameter" which has
> been introduced in the Verilog 2000/2001 Language (digital) which
> would also affect the analog side of things. I am assuming local
> parameter would become part of AMS language syntax definition too
> in the coming version of the LRM.
My working assumption is that there should be no unnecessary differences
between analog and digital Verilog, and that we have to follow what the
digital folks do. Parameter evaluation is part of elaboration, and is
done ahead of evaluating anything in actual simulation processes (analog
or digital), or A/D converter insertion.
> According to my understanding, local parameters are those
> that are used as constants, and cannot be overwritten.
> ie. something like the #defines at module scope. So these parameters
> can be defined inside a module and stay constant during simulation
> as well as set up time. My concern on local parameters
> is with regards to the parameter overrides while instantiating
> child modules. Local parameters cannot be overridden.
Is there a problem with the usage defined in 2000/2001? - If it is unclear
they should tidy it up. Under what conditions does it cause a problem for
Verilog-A[MS]?
Kev.
PS: IMO using order rather than name binding is a bad habit that should
stamped out :-)
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