Subject: Re: Overriding localparam value Issues
From: Pragmatic C Software (sjmeyer@pragmatic-c.com)
Date: Tue Feb 06 2001 - 19:28:51 PST
I was on the P1364 V2K committee and provide the digital engine for Antrim
Verilog AMS so let my try to explain the Verilog 2000
(aka v2k) parameter changes. First, they add no HDL functionality except
they prevent infinite regress for parameters used in new generate construct
where in a few contexts only localparam can be used. Without
this requirement, defparam value assignment and generate value assign can
conflict. Pound parameters can be used to control generate but use
of localparam simplifies generate processing. I have not gotten deeply
enough into the details of new generate to understand the exact localparam
requirements. The other main reason for addition of localparam is to
simplify elaboration and handle cases where, when designs are combined, the
parameters assigned to by defparams is undefined or at least very difficult
to determine. I do not think localparams effect Verilog AMS semantics.
The second change is that specify parameters are now allowed outside specify
section - in procedural blocks and I assume in analog block and in any analog
body instantiations. Initial value can be assigned by pound params but that
value can be changed by SDF (and other?) types of annotation. Specify
parameters can be assigned to module parameters (parameter stmt) although
depnding on the context the annotated specparam value may not change the
parameter value if the parameter has alrady been elaborated to a constant.
Module parametes can not be assigned to specify parameters (on rhs) although
I think initial specparam values can be set with pound parameters.
Finally, there are two new constructs related to parameters and back
annotation. First, any HDL object can have a "new" attribute with syntax
(* name=<value>, ... *). In AMS these could be annotated to if needed.
Second, much of the structural modifications that use parameters in Verilog
1995 use new configuration library feature in v2k. This features allows
controlling model selection including say selection of connect blocks.
Also configurations can control multiple passed of elaborations if that
is needed. It is simplified version of Cadence configuration feature.
/Steve
Quoting Kevin Cameron x3251 (Kevin.Cameron@nsc.com):
>
> > From: "Srikanth Chandrasekaran" <schandra@asc.corp.mot.com>
> > Subject: Overriding localparam value Issues
> >
> > Hi all,
> > This is regarding the feature "local parameter" which has
> > been introduced in the Verilog 2000/2001 Language (digital) which
> > would also affect the analog side of things. I am assuming local
> > parameter would become part of AMS language syntax definition too
> > in the coming version of the LRM.
>
> My working assumption is that there should be no unnecessary differences
> between analog and digital Verilog, and that we have to follow what the
> digital folks do. Parameter evaluation is part of elaboration, and is
> done ahead of evaluating anything in actual simulation processes (analog
> or digital), or A/D converter insertion.
>
> > According to my understanding, local parameters are those
> > that are used as constants, and cannot be overwritten.
> > ie. something like the #defines at module scope. So these parameters
> > can be defined inside a module and stay constant during simulation
> > as well as set up time. My concern on local parameters
> > is with regards to the parameter overrides while instantiating
> > child modules. Local parameters cannot be overridden.
>
> Is there a problem with the usage defined in 2000/2001? - If it is unclear
> they should tidy it up. Under what conditions does it cause a problem for
> Verilog-A[MS]?
>
> Kev.
>
> PS: IMO using order rather than name binding is a bad habit that should
> stamped out :-)
>
-- Steve Meyer sjmeyer@pragmatic-c.com
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