Subject: Re: Untimed behavioral Verilog-D & Connect modules
From: Jonathan Sanders (jons@cadence.com)
Date: Thu Feb 08 2001 - 23:55:19 PST
Kevin,
As far as I can tell all OOMRs must be given a full hierarchical path.
Thus the reason that we create a second top level block for these
references as we can then from any block give the path as shown
in my previous email on this.
Jon
At 05:26 PM 2/8/01, Kevin Cameron x3251 wrote:
>Marginally related to OOMR and "driver update" stuff.
>
>It crossed my mind that if I do have an "unreliable" driver
>(http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0004/)
>I may want to use a clock associated with the data and setup time
>specs instead. This is also related to where connect modules are
>placed (http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/)
>as it probably necessary to use an OOMR to reach the relevent clock.
>
>Is there an OOMR syntax equivalent of the Unix '..' ?
>
>Kev.
>
>--
>National Semiconductor
>2900 Semiconductor Drive, Mail Stop D3-677, Santa Clara, CA 95052-8090
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Jonathan L. Sanders
Product Engineering Director
Mixed Signal and Physical Verification Solutions
Cadence Design Systems, Inc.
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INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7265
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