Subject: Untimed behavioral Verilog-D & Connect modules
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Feb 08 2001 - 17:26:28 PST
Marginally related to OOMR and "driver update" stuff.
It crossed my mind that if I do have an "unreliable" driver
(http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0004/)
I may want to use a clock associated with the data and setup time
specs instead. This is also related to where connect modules are
placed (http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/)
as it probably necessary to use an OOMR to reach the relevent clock.
Is there an OOMR syntax equivalent of the Unix '..' ?
Kev.
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