Subject: Re: Untimed behavioral Verilog-D & Connect modules
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 12 2001 - 12:47:15 PST
> From owner-verilog-ams@eda.org Mon Feb 12 09:57:06 2001
>
> Quoting Kevin Cameron x3251 (Kevin.Cameron@nsc.com):
> >
> > > Kevin,
> > >
> > > As far as I can tell all OOMRs must be given a full hierarchical path.
> > > Thus the reason that we create a second top level block for these
> > > references as we can then from any block give the path as shown
> > > in my previous email on this.
> > >
> > > Jon
> >
> > I would suggest a syntax for "parent" if I could think of a good one
> > ('..' looks too much like a typo) - maybe '*' for a wildcard match?
> >
>
> There is already a mechanism in P1364 Verilog for "parent" references.
> They are called upward relative references. The first component can
> be either a module name or an instance name. The search rule is start
> by assumidesign first component is upward instance searching upward until root
> is seen. If not found, assume first component of name is module type name
> and repeat process, but again this feature is mostly avoided since it
> makes it harder for modules to be re-usable, i.e. the module needs to
> know the design context in which it is instantiated.
> /Steve
>
> <removed old messages>
>
> Steve Meyer
The problem is slightly more subtle in that automatically inserted (connect)
modules don't have a name for their parent module (assuming they are instantiated
under the driver/receiver process's module), they therefore need a symbolic name
for it.
Having thought about it, I would suggest "^", so "^.clock" from a connect module
refers to the signal "clock" in the parent. A blunter approach would be to allow
wildcards e.g. '*', as in '*.vdd' to connect the first instance of a signal vdd
in the hierarchy above.
Personally I would be happy with just "^" working only in connect modules.
This is a real problem at NSC, one of our mixed-signal simulation guys spent
weeks trying to create IEs in Opus that would change switch levels depending on
a varying VDD.
[Note: if connect modules are not attached under the module whose drivers/receivers
they serve then a symbolic name that refers to that module is required.]
Kev.
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