Subject: Minutes of AMS TC on Feb 6th 2001
From: Ian Wilson (imw@antrim.com)
Date: Thu Feb 15 2001 - 11:50:50 PST
Minutes of Verilog-AMS TC, Feb 6th 2001
The meeting commenced with a discussion on how best to make progress.
There is general agreement that while the current standard is useful,
we can improve it significantly by focusing on areas that are poorly
or ambiguously defined. The goal is to enable users to write models
that will be portable across implementations, and to enable vendors
to implement compliant tools.
We have identified some major issues that require work for the next
LRM revision. However, waiting for feedback on these isn't going to
be productive. Agreed that F2F technical session would be useful.
This is (currently) scheduled for the evening Thursday March 1st
(at or near HDLCon). The most significant areas at present appear
to be backannotation; the general approach to disciplines; and
levels of SPICE compatibility and mechanisms required to provide
these. We need to have one or two position papers to discuss at the
[during]HDLCon meeting. Actions: IMW, JS (discipline handling vs
use cases, e.g. multi-level logic). KC: need for backannotation.
Any, IMW: levels of SPICE support.
The meeting discussed deliverables and reconfirmed the following:
- 'Accelera 2.1' version in mid-2001
(improved definitions and reduced ambiguity - Verilog-D
compliance and VPI not significanltly changed from 2.0)
- 'IEEE' version in mid-2002
(has 2.1 as a starting point)
Following a suggestion by John Shields, the group discussed the
Design Objectives (accessible from eda.org). In summary:
- Verilog-AMS must be a superset of Verilog-200(1), not '95
- interoperability with VHDL1076.1 - the issue here is not
between multiple analog solvers but between digital and
analog kernel. John Shields proposed adopting the VHDL
synchronization semantics where appropriate. Needs review
- SPICE compatibility - DO calls for 'migration path'. It's
easy to import modules, very difficult to support some
netlist mechanisms. Needs review to determine what's
reasonable to expect from implementations [levels?]
- table models - promote from 'desirable' to 'should'?
- a/d events - could be expressed more clearly
- backannotation - missing from DO's, so not addressed in
LRM. Should this be (re)added to the DO's?
P1364-2000 reference: the TC needs to work with the most
up-to-date material, identified by Joe Daniels as Draft 6.
[This is now accessible to TC members - imw].
Most remaining issues on the Cadence issues list were discussed,
actions:
- 8.10.5(26) (netresolve()) agreed that explicit syntax is required
to express difference from Verilog-D net semantics. MO'L to propose
working syntax
- (27) (supplementary driver access functions). IMW to clarify
- (28) (which solver runs first?). Use Cadence diagram with P1364
terms; discuss role of initial() statements, etc, in 'initialization
bucket'
Upcoming meetings:
- teleconference Wednesday 2/21, 1:30pm PST - 4pm PST
(IMW to provide call-in numbers)
- working session Thursday March 1 at/near HDLcon, time
and place to be determined (NEED A COMPANY TO PROVIDE MEETING
ROOM please)
- informal dinner after working session
Ian Wilson Feb 14th 2001
This archive was generated by hypermail 2b28 : Thu Feb 15 2001 - 11:52:06 PST