Subject: Re: Reading Spice?
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 19 2001 - 15:46:41 PST
> Is anyone building a Verilog-A[MS] simulator that can't read Spice input?
I didn't get any negative responses on this, so I'll assume everyones
simulators can read (structural) Spice.
The follow-up questions are:
If we allow declaration of a junk of Spice as an external module,
can we use OOMRs to access nets in it from Verilog-A[MS]?
[NB: Verilog supports "escaped" names.]
and:
Can we use that mechanism with SPF to do explicit back-annotation
without re-netlisting?
Kev.
This archive was generated by hypermail 2b28 : Mon Feb 19 2001 - 15:52:24 PST