Subject: Spice Netlist Translation Requests
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Feb 21 2001 - 15:33:40 PST
Since it may be necessary to translate back and forward between
Verilog-A[MS] and Spice, I think we should definitely find a
namespace and make the Annex E Table E.1 official primitives of
Verilog-A[MS]. Any parameters that can't be agreed on should be
passed by attributes, and any primitives we can't agree on will
be left until we have an accepted primitive declaration mechanism.
A couple of additional requests are:
1. It would be nice to be able to use a translated
netlist in a regular Verilog-D simulator using the
ntrans/ptrans primitives through macro modules. So
n & p channel devices should have seperate names
rather than a common name (i.e. we should have nmosfet
and pmosfet rather than just mosfet).
2. An analog designer told me once that one of the
things that often causes differences between simulation
and Silicon is the use of multi-drain/source and
multi-emitter/collector structures which are not
representable in Spice. It would be nice to have a syntax
that expresses that usage e.g.:
// current mirror - ref on d1
nmosfet n1 (.d[0](d1),.d[1](d2),.s(vss),.g(d1));
[ I would have added attributes for drain area - but I
can't remember the syntax ]
Kev.
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