Subject: RE: Spice Netlist Translation Requests
From: Ian Wilson (imw@antrim.com)
Date: Thu Feb 22 2001 - 11:18:25 PST
>
>
> Since it may be necessary to translate back and forward between
> Verilog-A[MS] and Spice, I think we should definitely find a
> namespace and make the Annex E Table E.1 official primitives of
> Verilog-A[MS]. Any parameters that can't be agreed on should be
> passed by attributes, and any primitives we can't agree on will
> be left until we have an accepted primitive declaration mechanism.
>
Verilog-AMS at present doesn't add any primitives to the language.
Adding them at this stage would require detailed definition of where
such primitives could be used, what their connection rules are,
whether analog UDPs can be written, etc... This seems like a lot of
extra work at this stage of the language's life.
Parameters: note that the SPICE treatment of default values is quite
different from Verilog's (SPICE makes use of the fact that no value
has been specified for a parameter to interpret other parameters).
--ian
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