Subject: Re: Issue 17: Filters for foreign languages
From: Jonathan Sanders (jons@cadence.com)
Date: Mon Feb 26 2001 - 07:50:55 PST
Kevin,
While I don't think it made it in the LRM the discussion on this was always
to use Verilog wrappers to allow users to map between various SPICE syntax's.
Wrappers are very common in Verilog and used to build ASIC libraries from
primitives as well as by vendors for cross language boundaries like VHDL in
Verilog.
Users or Vendors can create these and they work with the existing language
without changes. Let's take the HSPICE resistor model:
Rxxx n1 n2 mname R=val TC1=val TC2=val SCALE=val M=val AC=val
+ DTEMP=val L=val W=val C=val
And I have a Verilog netlist that instantiates this as follows:
resistor #(.r(1k), .tc1(.005), .tc2(.003), .m(3), .dtemp(100)) r1(out, gnd);
If I select my HSPICE to Spectre templates I would use the following wrapper:
module resistor (p, n);
inout p, n;
electrical p, n;
parameter real r = 1 exclude 0.0;
parameter real tc1 = 0.0;
parameter real tc2 = 0.0;
parameter real scale = 1.0;
parameter real m = 1.0;
parameter real ac = 0.0;
parameter real dtemp = 0.0;
parameter real w = 0.0;
parameter real l = 0.0;
parameter real c= 0.0;
real res;
// map the parameters that are different between HSPICE and Spectre
// either with syntax mapping or with code change mapping as needed
analog begin
if analysis("ac") begin
if (ac != 0.0) res = ac * scale / m;
else res = r * scale / m;
end
else res = r * scale / m;
if (c != 0.0 ) V(b) <+ ddt(V(b)) / c ;
else I(b) <+ 0.0;
end
resistor #(.r(res), .tc1(tc1), .tc2(tc2), .m(m), .trise(dtemp), .w(w),
.l(l) ) r1(a, b);
endmodule
Each vendor supports a different flavor of SPICE, some closer than others,
some
not SPICE, this mechanism gives the interested part the ability to support
other syntax's as much as possible. This does in most cases add a layer of
hierarchy but for compatibility support I find that to be a reasonable
tradeoff.
Do you see problems in this method since it was what the committee talked
about doing many months ago even though it was not written down in the LRM?
Jon
At 11:27 AM 2/22/01, Kevin Cameron x3251 wrote:
>Here is where to find the "filters" proposal -
>
>http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0017/
>http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/
>
>Let me know if I missed anything or if you have an alternative
>syntax proposal (I'm not sure overloading the extern-module
>definition was a good idea).
>
>Kev.
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