Subject: Dynamic/Global Parameters in Verilog-AMS
From: Martin O'Leary (oleary@cadence.com)
Date: Fri Feb 23 2001 - 17:49:07 PST
here is the write-up I promised last Wednesday,
--Martin
Dynamic/Global Parameters in Verilog-AMS
==============================================
--Martin O'Leary 2/23/2001
Terminology
-----------
OOMR: Out-of-module reference
e.g. $strobe(top.foo.param1)
top.foo.param1 is an OOMR to param1 in the instance foo in the top module.
Motivation
------------
1) references to global parameters
In analog simulation, it is also a common feature to be able to
reference global parameters without having their values passed down
through the hierarchy. Such parameters can refer to quantities such
as temperature, or process dependent parameters which are shared
by a large number of devices in a design.
These references can be in default parameter expressions or
is parameter expressions assigned to instances.
Verilog HDL and Verilog-AMS have no concept of a global
parameter. However they do have the concept of an out-module-
reference to a OOMR parameter.
To get the same effect as global parameters, all parameters
that are desired to be global can be placed in the same
module, e.g. "module globals", and referenced from there
using OOMRs. However this still does not give all the
functionality required, because although OOMRS
to parameters are allowed in module instance parameter
assignment expressions, OOMRS are not allowed in
parameter default value expressions, defparam value (i.e.,
right hand side) expressions.
For an analog model developer, this makes the previous
modelling style impossible.
For Verilog-AMS to be acceptable to the analog community, it
needs to be enchanced to support OOMR parameter references in
defparam value expressions.
2) ability to alter parameters
In analog simulators, it is also common feature to be able to change the
value of a parameter during simulation and for the effect of that
parameter change to propagate to all parameters depending on that parameter
change.
This functionality is used to support dc sweeps, multiple transient
simulation in the same simulation run, and Monte-Carlo analysis.
The advantage of the being able to alter a parameter during an
analog simulation is that the simulator doesn't have to be shut down
and source netlist doesn't have to be regenerated. This leads to a
considerable time saving for the user.
Verilog HDL contains no support for parameter alteration during simulation
time. Verilog-AMS currently contains no such support either.
For Verilog-AMS to be accepted as a viable analog simulation language,
Verilog-AMS needs to support some mechanism for supporting parameter
alteration at simulation time.
Proposal
--------
To address the two major issues raised in the motivation, a new
type of parameter is proposed for Verilog-AMS called a dynamic
parameter.
* They will be indicated by the keyword, "dynamicparam"
* Syntactically dynamic parameter declarations are the same as
parameter declarations except for the dynamicparam keyword;
module foo;
dynamicparam real p1 = 5.0;
* Dynamic parameters can be used everywhere that parameters can be used.
* Dynamic parameters are set like normal parameters.
* However OOMR references to dynamic parameters will be allowed
in defparams.
module top();
dynamicparam myvar = 0.133;
Boo B1;
...
...
endmodule
module Boo
Foo F1;
defparam top.B1.F1.param1 = top.myvar*3; // defparam usages
endmodule
* Although OOMR references will not be allowed in parameter
assignments. The reason for this is that the default values
for a module must be calculatable before the hierarchy is
elaborated. However the same effect can be achieved by having
a local defparam.
module Foo();
parameter param1 = 0;
defparam param1 = top.myvar*2; // equivalent to allowing
// defparams to default parameter values
endmodule
* Dynamic parameters are evaluated as part of the normal parameter
evaluation process as if they were normal parameters.
* It is illegal for a parameter value that is dependent on dynamic
parameters to affect design topology.
Note: a parameter is dependent on a dynamic parameter if the value
of a dynamic parameter had an affect on the final computed value of
that parameter.
* It is illegal for a parameter value that is dependent on dynamic
parameters to be referenced from a digital context. This is so as to
have the least impact on existing Verilog engines used to support
AMS simulators. The restriction could be dropped in a later Verilog-AMS
language revision.
* Simulators may support a mechanism to change dynamic parameters
at the start of a simulation/analysis without having to edit
a design.
In this case all parameter values dependent on the dynamic parameter
will be recalculated.
The calculated values must be the same as that that would have been
calculated if an extra defparam had been applied to the dynamic parameter
at the end of parameter calculation process during elaboration.
The dynamic parameters are set once before the start of an analysis, and
are then constant during the simulation of the analysis.
Example:
module global_params
dynamicparam rfactor=1.2;
endmodule
module top;
electrical p,n;
vsource #(.type("dc"), .dc(5)) S1(in,ground);
resistor R1(in.out);
defparam R1.r = 1k * global_params.rfactor;
capacitor #(.c(1u)) C1(out,ground);
rchain #(.rf(globals_param.rfactor*1.001)) R2(out,ground);
defparam R1.r = 1k * global_params.myvar;
endmodule
module resistor(p,n);
electrical p,n;
parameter r = 1k;
....
endmodule
module capacitor(p,n);
.....
endmodule
module rchain(p,n);
parameter rf = 0;
defparam rf = global_params.rfactor;
electrical p,n;
resistor #(.r(3k*rf)) RA(p,n);
resistor #(.r(2k*rf)) RB(p,n);
endmodule
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