Subject: Re: Issue 17: Filters for foreign languages
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 26 2001 - 10:26:47 PST
>
> Kevin,
>
> While I don't think it made it in the LRM the discussion on this was always
> to use Verilog wrappers to allow users to map between various SPICE syntax's.
> Wrappers are very common in Verilog and used to build ASIC libraries from
> primitives as well as by vendors for cross language boundaries like VHDL in
> Verilog.
>
> Users or Vendors can create these and they work with the existing language
> without changes. Let's take the HSPICE resistor model:
>
<Example deleted>
> Each vendor supports a different flavor of SPICE, some closer than others, some
> not SPICE, this mechanism gives the interested part the ability to support
> other syntax's as much as possible. This does in most cases add a layer of
> hierarchy but for compatibility support I find that to be a reasonable tradeoff.
> Do you see problems in this method since it was what the committee talked
> about doing many months ago even though it was not written down in the LRM?
>
> Jon
Layers of extra hierarchy and keeping translated files are a headache (particulary
large files like SPF).
All the "filter" proposal suggests is a mechanism for running the "wrapper/translator"
as part of pre-processing so that it is more transparent and doesn't require
extra disk space.
E.g. in our extraction flow when we produce a multi-gigabyte SPF file, I could
create a Verilog-AMS wrapper module:
extern module SPF;
parameter source = "/prij/big_chip/extracted/chip.spf.bz2";
parameter language = "SPF";
parameter filter = "spf2vams -compressed=bzip2";
endmodule
- and I'm done: no looking for extra disk space, no need to run 'spf2vams' unless
it is actually needed.
Ease of use = quicker adoption.
Kev.
PS: I added a follow-up on the original proposal -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0017/fllwup-1.html
> At 11:27 AM 2/22/01, Kevin Cameron x3251 wrote:
>
> >Here is where to find the "filters" proposal -
> >
> >http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0017/
> >http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/
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