Subject: Re: Attributes
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 26 2001 - 09:42:24 PST
> From jons@cadence.com Mon Feb 26 09:06:50 2001
>
> Ian,
>
> Attributes have existed since the days of XL but are now being formalized in
> Verilog 2001. I believe the primarily purpose is to use this feature as a method
> to implement vendor independent features. I know we use it and I believe the
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Don't you mean vendor/tool specific?
My feeling is that stuff that we can't agree on that can be done by using
attributes should probably turn up as "recommended usage" somewhere (for
the time being).
> examples I have seen have been for Synopsys synthesis properties. It certainly
> was not intended as a prototyping mechanism although that may be a way that
> some vendors use it.
IMO it's a good mechanism for prototyping. If user/vendors can present a
working system using attributes, it demonstrates both a need and a methodology
we can work on formalizing.
Kev.
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