Subject: Back Annotation Proposal
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Mar 14 2001 - 12:07:42 PST
Here is a proposal for back-annotation in Verilog-AMS -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/back_ann.pdf
NB: even if nobody intends to implement this anytime soon we
need to define a mechanism and make sure it will work with
whatever Verilog-AMS 2.1 does. Vital held up VHDL adoption
for a considerable time, and it was required because issues
like back-annotation were not considered properly in the
original design of VHDL (or VHDL-A for that matter).
Kev.
PS: I'm updating the PDFs in place rather than creating versions
and sending more e-mails.
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