Subject: RE: ...digital variable access
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Mar 21 2001 - 13:07:04 PST
> From owner-verilog-ams@eda.org Wed Mar 21 12:41:15 2001
....
>
>
> Note also that r changes discontinuously in the above example, so for it
> to be usable in contributions, etc, you have to condition it:
>
> wire w;
> real r;
> electrical out;
> analog begin
> r = w;
> V(out) <+ transition(5.0 * r, ....);
> end
>
> The levels (0 to 5) and rise/fall times are provided by the user
> explicitly in the behavioral code here, and are not related to any
> connect module or discipline.
>
> --ian
Are you implying that the analog process is evaulated when 'w' changes?
Should it be explicit? -
...
analog begin
@(w) r = w;
V(out) <+ transition(5.0 * r, ....);
end
- and would that be equivalent to using 'wreal' in :
wire w;
wreal r;
always @(w) r = 5.0 * w;
analog V(out) <+ transition(r, ....);
- not that I like wreal :-)
Kev.
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