Subject: Re: Workgroup status (II)
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Wed Mar 28 2001 - 16:08:25 PST
Reply To: schandra@asc.corp.mot.com
Organization: Motorola Australia Software Center
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Ian,
Just two more issues that were discussed but is not part of
the workgroup...
1. Does this mean that "Discipline Resolution" has been resolved
or it is not being addressed in the next version? There were lots
of discussions, and we have some idea (which we can submit as
a proposal), which we could discuss on.
2. How about handling of verilog and spice primitives which is
not addressed in the current LRM.
regards,
Sri
Ian Wilson writes:
#
#So far the responses that I have had have mostly been related to the
#initialization/simulation cycle; also, recent emails on cross domain
#access and synchronization have been very useful.
#
#Proposal for work groups and members:
#
# 1. Mixed signal initialization and simulation cycle (including
# alignment with VHDL-AMS semantics): Peter, Dan, Martin
#
# 2. Semantics and synchronization of cross-domain access: Ian,
# Martin, Graham
#
#Deliverables: statement of the issues and what the group expects
#to provide for resolution. If possible I'd like to have this
#available for a phone meeting some time next week (4/2 - 4/6).
#
#Please contact me if you are in one of the two workgroups (or
#would like to be, or would like to initiate a new one).
#
#Thanks,
#
#--ian (still operating at about 20% here)
#
#
-- Hard work may not kill you, but why take chances?Srikanth Chandrasekaran EDA Solutions and Products SBU Phone: +61-8-8203 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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