Subject: Re: Workgroups (III) contd
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Apr 06 2001 - 14:42:47 PDT
> From owner-verilog-ams@eda.org Fri Apr 6 13:50:26 2001
>
> Ran out of time, sorry. If possible, over the next 2 weeks, could each
> workgroup make internal contact and come up with a paragraph stating
> what they expect the scope of the effort to be. It would be useful if
> they would identify existing material, and anything else relevant would
> be useful.
>
> Regarding backannotation: it would be helpful if the protagonists could
> dig up the mechanism that will be necessary if we decide to add to the
> Design Objectives. It would be very useful if any mixed signal designers
> out there experienced with tools/flows for backannotation could provide
> some input for us.
The data for back-annotation is SPF/SPEF, which is basically Spice netlist,
and we need to have a fairly well defined mechanism to translate Spice (like)
netlists into Verilog-A anyway (see issues 17 & 19), so I'm assuming that
we take that translated netlist and patch it into the un-annotated design in
a similar manner to SDF (i.e. not disturbing the namespace). A possible
patching mechanism is outlined in the document -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/back_ann.pdf
- and is mostly just tweaking the "actuals" in module instantiation during
elaboration.
Problems with rewiring a mixed analog/digital design to include parasitics
and extra components are mostly associated with using port-bound disciplines
(see issue 2, follow-up 2), which assume particular hierarchical relationships
and place A/D convertors incorrectly (issue 3).
Kev.
[ Issues are at http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/ ]
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