Subject: Re: Discipline Resolution for Analog/Digital Primitives
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed May 09 2001 - 10:43:51 PDT
Jonathan Sanders wrote:
>
> Sri,
>
> Still absorbing this proposal but one thing I did not see that needs to be
> covered. Digital primitives if we are to add them back into the LRM must
> have port names defined for them. This is also true for analog primitives
> and part of the reason for the SPICE annex although even in a generic
> sense SPICE primitives should have names. Anyway back when digital
> primitives were supported (for parasitic backannotation) there was a naming
> mechanism provided in the LRM for them and I am providing it below for
> inclusion if digital primitives are coming back.
>
> Port Names for Verilog Built-in Primitives
> In the cases of instances of modules and instances of UDPs port names are well defined.
> In these cases the port name is the name of the signal at the lower connection of the port.
> in the case of built in primitives, however, Verilog-D does not define port names. It is,
> thus necessary to define port names for the ports of built in primitives in Verilog-AMS.
> The following conventions will be used for naming Verilog Ports.
> 1. For N-input gates (and, nand, nor, or, xnor, xor) the output will be named out, and the
> inputs reading from left to right will be in1, in2, in3, etc.
> 2. For N-output gates (buf, not) The input will be named in, and the outputs reading
> from left to right will be named out1, out2, out3, etc.
> 3. For 3 port MOS switches (nmos, pmos, rnmos, rpmos) the ports reading from left to
> right will be named source, drain, gate.
> 4. For 4 port MOS switches (cmos, rcmos) the ports reading from left to right will be
> named source, drain, ngate, pgate.
> 5. For bidirectional pass switches (tran, tranif1, tranif0, rtran, rtranif1, rtranif) the ports
> reading from left to right will be named source, drain, gate.
> 6. For single port primitives (pullup, pulldown) the port will be named out.
>
> One reason for port names is for the unique name given each connect module. In
> the detail mode the port name is used.
> Jon
As I said to Sri & Graham (although the message doesn't appear to have reached
the reflector), there is an initial proposal for "representation stops" on
the issues page:
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0019/index.html
- as it stands it doesn't include anything about port disciplines, but could
be extended to cover that. It does cover the port naming problem.
The proposals linked on the issues page are for review/feedback - feel free
to comment, I'll be happy to rehash them to cover issues that have been missed.
For [n]and/or/xor gates with multiple inputs I would prefer an 'in[*]' (i.e. in[0],
in[1],...) syntax in the rep-stop specification so that we don't have to do
the cases individually - e.g. the last port listed in a rep-stop can be an unsized
array and it is sized on instantiation.
Kev.
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