Subject: RE: Real valued nets.
From: David Smith (david_smith@avanticorp.com)
Date: Wed Aug 22 2001 - 09:56:04 PDT
This is all fine but in future versions of Verilog there will be support for having ports of type real (the complete list is wire, interface, event, or variable - variable covers a lot more ground than in current Verilog). Why not just support what we need now. I also do not understand the rational for 'wreal'. Seems unnecessary. The issue then becomes of what happens when an analog wire is connected to a port of type real. This seems definable.
Regards
David
-----Original Message-----
From: Kevin Cameron x3251 [mailto:Kevin.Cameron@nsc.com]
Sent: Tuesday, August 21, 2001 1:17 PM
To: verilog-ams@eda.org
Subject: Re: Real valued nets.
(Thoughts for discussion)
One of differences between analog and digital is that
signal values are deemed "continuous" in analog but
"discrete" in digital. However, the "continuous"
signals are actually mostly piecewise-linear (the
first derivative w.r.t. time is discrete), a
"digital" simulator which can schedule in real time
can therefore support most analog waveforms. Only
analog processes require the support of an equation
solver, digital processes should be able to schedule
piecewise-linear waveforms and read them back in the
absence of a solver.
So, rather than define all the semantics for 'wreal'
I would suggest just using "analog" value of a wire.
If folks do want to keep 'wreal' then I suggest that
it be identical to a wire of the default discipline
and that it's read value is the potential to ground,
and writing to it sets the potential immediately.
Note: setting the potential directly would cause
discontinuities, but if the net is not used by any
analog process that would not matter. If the net
has any analog contributions or receivers then a
D->A connect module would be inserted and the digital
process driving value etc. should be available through
driver access functions.
Regards,
Kev.
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