Subject: RE: Real valued nets.
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Wed Aug 22 2001 - 11:02:49 PDT
> From owner-verilog-ams@eda.org Wed Aug 22 10:11:19 2001
> From: "David Smith" <david_smith@avanticorp.com>
>
> This is all fine but in future versions of Verilog there will be support for having ports of type real (the complete list is wire, interface, event, or variable - variable covers a lot more ground than in current Verilog). Why not just support what we need now. I also do not understand the rational for 'wreal'. Seems unnecessary. The issue then becomes of what happens when an analog wire is connected to a port of type real. This seems definable.
>
> Regards
>
> David
If you want to do mixed analog/digital sampled data systems then you
probably want to be able to use real-valued nets, but sampled
data systems don't need analog solvers e.g. an ethernet chip that
I saw recently had some echo-cancelling circuits that could be
modelled easily with piecewise-linear signals.
My view is that just defining 'wreal' as being equivalent to an
analog wire (of default discipline) with limited syntax and
semantics, makes it a minimal extension to the language. Which
will avoid us having to argue about its existance and what its
semantics should be.
Regards,
Kev.
> -----Original Message-----
> From: Kevin Cameron x3251 [mailto:Kevin.Cameron@nsc.com]
> Sent: Tuesday, August 21, 2001 1:17 PM
> To: verilog-ams@eda.org
> Subject: Re: Real valued nets.
>
>
> (Thoughts for discussion)
> ....
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