Subject: RE: Real valued nets.
From: David Smith (david_smith@avanticorp.com)
Date: Wed Aug 22 2001 - 12:46:11 PDT
What I am missing here is the reason for real-valued nets. If I have the ability to pass real data through ports and connect them then why is a net important. I can clearly do sampled data systems using this. The underlying issues are:
1. support for conservative connection semantics
2. support signal flow (continuous time, continuous value) semantics
3. support for event driven semantics (discrete time, continuous or discrete value)
The piece missing from Verilog-AMS is event drive semantics of continous real value on connections. This does not require a new net type. Just the support of connections of variables (real) in addition to nets.
Wreal has no place in this (at least it is not a definition of anything that does not exist if the support for real variable connections is added).
Instead of arguing through this lets wait until Jon and I generate our proposal. He may help me to see the error of my ways.
Regards
David
-----Original Message-----
From: Kevin Cameron x3251 [mailto:dkc@galaxy.nsc.com]
Sent: Wednesday, August 22, 2001 11:03 AM
To: verilog-ams@eda.org
Subject: RE: Real valued nets.
> From owner-verilog-ams@eda.org Wed Aug 22 10:11:19 2001
> From: "David Smith" <david_smith@avanticorp.com>
>
> This is all fine but in future versions of Verilog there will be support for having ports of type real (the complete list is wire, interface, event, or variable - variable covers a lot more ground than in current Verilog). Why not just support what we need now. I also do not understand the rational for 'wreal'. Seems unnecessary. The issue then becomes of what happens when an analog wire is connected to a port of type real. This seems definable.
>
> Regards
>
> David
If you want to do mixed analog/digital sampled data systems then you
probably want to be able to use real-valued nets, but sampled
data systems don't need analog solvers e.g. an ethernet chip that
I saw recently had some echo-cancelling circuits that could be
modelled easily with piecewise-linear signals.
My view is that just defining 'wreal' as being equivalent to an
analog wire (of default discipline) with limited syntax and
semantics, makes it a minimal extension to the language. Which
will avoid us having to argue about its existance and what its
semantics should be.
Regards,
Kev.
> -----Original Message-----
> From: Kevin Cameron x3251 [mailto:Kevin.Cameron@nsc.com]
> Sent: Tuesday, August 21, 2001 1:17 PM
> To: verilog-ams@eda.org
> Subject: Re: Real valued nets.
>
>
> (Thoughts for discussion)
> ....
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